Memory arrays formed from static random access memory (“SRAM”) cells are commonly used in many different applications. Such arrays are typically configured into multiple columns of cells with each column of cells sharing a common bit line. For example, with so-called “6T” SRAM cells, which have a pair of complementary storage nodes, a common, complementary bit line pair is commonly utilized. It is typically controllably coupled (e.g., through gate or access transistors) to a relatively large number of cells in a column. When a cell is to be read, the bit line pair is charged to a High level during a precharge state. Next, during an evaluate state, a selected cell to be read is activated (coupled to the bit line pair with its gate transistors turned on) causing one of its bit lines to discharge into a Low node of the selected cell. Unfortunately, in some cases, the bit line discharges in a way that causes the cell to be improperly read. Accordingly, this disclosure provides solutions for addressing such read instability problems.